NXP Semiconductors /LPC11Axx /SYSCON /WDTOSCCTRL

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Interpret as WDTOSCCTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DIVSEL0 (OPERATION_IS_UNDEFIN)FREQSEL0RESERVED

FREQSEL=OPERATION_IS_UNDEFIN

Description

Watchdog oscillator control

Fields

DIVSEL

Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64

FREQSEL

Select watchdog oscillator analog output frequency (Fclkana).

0 (OPERATION_IS_UNDEFIN): Operation is undefined for this value. Startup code should program a non-zero value in this field as soon after reset as possible.

1 (0_6_MHZ): 0.6 MHz

2 (1_05_MHZ): 1.05 MHz

3 (1_4_MHZ): 1.4 MHz

4 (1_75_MHZ): 1.75 MHz

5 (2_1_MHZ): 2.1 MHz

6 (2_4_MHZ): 2.4 MHz

7 (2_7_MHZ): 2.7 MHz

8 (3_0_MHZ): 3.0 MHz

9 (3_25_MHZ): 3.25 MHz

10 (3_5_MHZ): 3.5 MHz

11 (3_75_MHZ): 3.75 MHz

12 (4_0_MHZ): 4.0 MHz

13 (4_2_MHZ): 4.2 MHz

14 (4_4_MHZ): 4.4 MHz

15 (4_6_MHZ): 4.6 MHz

RESERVED

Reserved

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